1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Related Art
In recent years, a lower resistance material such as copper and the like has become utilized as an interconnect material, from the requirements for the operating velocity of the semiconductor device.
A damascene process includes a single damascene process for forming only an interconnect with damascene process, and a dual damascene process in which a connection plug and an interconnect are made to form upon conducting also embedding of a connection hole and an interconnect trench.
FIGS. 18A to 18E are cross-sectional views showing a method for forming a connection plug and an interconnect by the dual damascene process. FIG. 18A is a process sectional diagram of a step of forming a first metal interconnect containing copper 220a. There is described the process up to the state of FIG. 18A. Firstly, a first silicon nitride film 212 and a first silicon oxide film 214 are formed on a semiconductor substrate 210 on which an element such as a transistor or the like is formed, after that, a interconnect trench is made to form by dry etching, a barrier metal film 216a and a copper containing metal film 218a are formed in this order so as to embed its inside. After that, the first copper containing metal interconnect 220a is formed upon conducting planarization by a CMP process. Next, a second silicon nitride film 222 and a second silicon oxide film 224 are formed. Thus, a state of FIG. 18A is accomplished.
Next, as shown in FIG. 18B, in the second silicon oxide film 224, a connection hole 226 for a connection plug and a interconnect trench 228 are formed by a lithography technique and an etching. Successively, the etching of the second silicon nitride film 222 is carried out while changing an etching gas. After that, as shown in FIG. 18C, a barrier metal film 230 is entirely formed on the second silicon oxide film 224 containing the connection hole 226 and the interconnect trench 228.
Next, as shown in FIG. 18D, a copper containing metal film 232 is formed on the barrier metal film 230 so as to embed the connection hole 226 and the interconnect trench 228. Next, as shown in FIG. 18E, the planarization by the CMP is performed so as to remove the copper containing metal film 232 and the barrier metal film 230 at the portion other than the interconnect trench 228, owing to this, a connection plug 234 and a second copper containing metal interconnect 220b are formed.
By repeating one series of processes described above, the semiconductor device including a multilayer structure is formed.
However, in the semiconductor device obtained by conventional dual damascene process, since there is provided a barrier metal film between the connecting plug and a lower layer interconnect, there was still room for further improvement in aspect of conductivity between the connecting plug and the lower layer interconnect.
Accordingly, there is disclosed a technique for manufacturing the semiconductor device by the dual damascene process without providing a barrier metal film between the connecting plug and the lower layer interconnect (Japanese Laid-Open Patent Publication NO. 1998-284603). In this technique, such structure schemes reduction of resistance between the connection plug and the lower layer interconnect.
Further, there is also disclosed a technique for forming a barrier metal film at a sidewall of a connection hole and an upper layer interconnect while removing the barrier metal film provided at the bottom of the connection hole that is the technique for manufacturing the semiconductor device by the dual damascene process without providing the barrier metal film between the connection plug and the lower layer interconnect (Japanese Laid-Open Patent Publication NO. 2001-284449). This technique schemes to lessen an electro migration by such manufacturing method.